Many semiconductor circuits require the switching of high voltages. For example, floating gate non-volatile memory devices require voltages to erase and program the memory device that are significantly higher than the voltages needed for other device functions, such as reading data from the memory or communicating with other semiconductor circuits. Thus, semiconductor circuits often employ a voltage conversion circuit to provide the high voltage levels required by the non-volatile memory and other associated devices. The use of such high voltages, however, leads to the possibility of snapback or breakdown, both of which are extremely undesirable.
Snapback occurs in some metal oxide semiconductor (MOS) transistors if a large voltage difference exists between drain and source (Vds) and the gate voltage (Vgs) is sufficient to cause a drain current (Ids) to flow that is above a certain threshold. High acceleration fields close to the drain region create electron-hole pairs and, in the case of n-channel transistors, holes flowing into the substrate can cause an increase in voltage near the source region. If the voltage increase is sufficient to forward bias the source junction, then additional carriers are injected into the substrate and the npn transistor formed by the source and drain junctions becomes highly conductive. The npn transistor current creates additional electron-hole pairs and, if the current gain of the bipolar structure is greater than one, the cycle is regenerative and snapback is said to occur. Once snapback occurs, the gate voltage ceases to control current flow and circuit functionality can be lost or the device can be destroyed.
Different transistor fabrication processes have different limits for the conditions that initiate snapback. In one exemplary transistor technology, the Vds and Ids limits that initiate snapback are 5V (Vds_sb) and 10 nA/μm (Ids_sb), respectively. Thus, to avoid snapback, the voltage between drain and source should be less than Vds_sb. Alternatively, if a high Vds cannot be avoided and Vds is greater than Vds_sb, then snapback can be avoided by limiting the drain/source current to a value less than Ids_sb. In this case, the source region does not become sufficiently forward biased to inject current into the substrate. However, imposing a limit of only 10 nA/μm is too restrictive for most practical circuits. Either the current would need to be very small and performance would be compromised, or the transistor width would need to be overly large, resulting in an increase in die size.
Furthermore, during the production testing of non-volatile memories it is a common requirement to switch a relatively high current that is sourced from a high voltage supply. While currents from the high voltage source may be low during normal operation, the currents can be much higher during certain test modes during production testing when many cells are written simultaneously. For instance, for the exemplary transistor technology, the load presented by the memory cell is mainly capacitive during an erase operation and requires only a few microamps from the high voltage supply during a program operation. In normal modes, only a few bits or a small number of bytes are being written at any one time and an internal charge pump is able to provide the high voltages and currents. During test modes, however, in order to reduce the time required to test the memory, a large number of cells (on the order of thousands) are written simultaneously and the current demand is increased by a factor approximately equal to the increase in the number of cells being written. The current required from the high voltage supply may now be beyond the capability of the on-chip charge pump and an external supply needs to be connected to either assist or replace the charge pump.
In addition to the exemplary transistor technology, circuits using other transistor technologies or circuits without an on-chip charge pump may also make use of a switched external high voltage supply. Even in memories that do not use a direct current to program cells, it may be desirable to connect a low impedance high voltage source to allow charge up of the large capacitances associated with “mass mode” tests in a short time period. Other memory types may require high currents to write data in a normal mode. Thus, it is a common practice to connect an external high voltage supply to a connection terminal (pad) of the semiconductor circuit, such supply being used to erase or program the non-volatile memory (or both).
The external high voltage supply available on low-cost production testers is often limited to a simple direct current (DC) supply. In contrast, the internal supply that is required to write to the memory is more complex and must be switched, alternately high and low, often with ramp rates and timing relationships that are controlled by a combination of tester and internal control signals.
Thus, a need exists for on-chip circuits that are capable of switching and controlling high voltages, sometimes with high current, without inducing snapback. A further need exists for a method and apparatus for switching high voltages and high currents, if necessary, without inducing snapback or breakdown. Another need exists for a method and apparatus for switching high voltages and high currents, if necessary, for example, during accelerated testing of non-volatile memory semiconductor circuits.